1. Field of the Invention
This invention relates to programmable integrated circuits, and in particular, the present invention relates to techniques for programming multiple programmable devices simultaneously.
2. Discussion of the Related Art
Programmable devices that can be programmed and reprogrammed without being removed from its application environment are widely preferred because programming and reprogramming of such devices can be performed with ease. One type of such devices is the "In-system programmable logic devices" or "ISP PLDs", available from Lattice Semiconductor Corporation. (To simplify reference, in the following description, such and similar devices are all referred to as "ISP PLDs". It should be understood, however, that the teachings in the following description are applicable to all types of field programmable devices, including programmable logic devices, programmable memories, and programmable analog circuits). The design and use of ISP PLDs are disclosed in the prior art, e.g. (i) U.S. Pat. No. 5,329,179 entitled "Arrangement For Parallel Programming Of In-system Programmable IC Logical Devices", to Tang et al, filed on Oct. 5, 1992 and issued on Jul. 12, 1994. (ii) U.S. Pat. No. 5,237,218, entitled "Structure and Method for Multiplexing Pins for In-system Programming", to G. Josephson et al, filed on May 3, 1991 and issued on Aug. 13, 1993; (iii) U.S. Pat. No. 4,879,688, entitled "In-system Programmable Logic Devices" to Turner et al, filed on May 13, 1986, issued on Nov. 7, 1989; and (iv) U.S. Pat. No. 4,855,954, entitled "In-system Programmable Logic Device with Four Dedicated Terminals" to Turner et al, filed on Oct. 25, 1988, and issued on Aug. 8, 1989.
In the prior art, each ISP PLD in a system board containing multiple ISP PLDs is individually and sequentially programmed. To program multiple ISP PLDs simultaneously requires both additional hardware and special configurations of the ISP PLDs. For example, where simultaneous programming of multiple ISP PLDs is possible, additional circuits for signal multiplexing are typically required. When devices in an application are programmed individually and sequentially, the devices to be programmed are chained serially and hence the total programming time of the serial chain of devices is the sum of the times required to program each device individually.
An ISP PLD contains a large number of programmable logic components, e.g. the "min-terms" of a programmable gate array. In some ISP PLDs, a linear address space is provided, and the programmable logic components of an ISP PLD are programmed in ascending address order until all the programmable logic components of the entire ISP PLD are programmed. Thus, even when simultaneous programming is provided, the total programming time of a system board is often determined by the sum of the time required to program that ISP PLD on the system board which has the most number of programmable components, and the time required to send data to all the ISP PLDs of the serial chain.
In the prior art, a "programming command generator" is given a data file which contains only the pattern necessary to program the ISP PLDs on a given system board. The programming command generator derives from the data file all the device dependent parameters, and provides the commands for the programming to occur.